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Hardware Architecture Design with FPGA - 4AMCE410

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  • Number of hours

    • Lectures : 12.0
    • Tutorials : 6.0
    • Laboratory works : 9.0
    • Projects : -
    • Internship : -
    • Written tests : -
    ECTS : 2.5
  • Officials : Vincent BEROULLE

Goals

At the end of the lecture, the students will be able to design complex digital systems into programmable components (CPLD ou FPGA)

Content

Lecture chapters

  1. Introduction
    1. Programmable components
    2. Context and issues
    3. Design flow
    4. Signal vs. variable
    5. Why to use programmable components ?
  2. Design of synchronous digital systems and GALS
    1. GALS design
    2. Metastability and signal transmission between clock domains
  3. Methods for RTL Synthesis
    1. Synthesis directives issues (ressources sharing, FSM coding...)
    2. Regular design
    3. Random design (FSM-based descriptions)
    4. RTL design : from flow chart to ASMD
  4. Digital Signal Processing with FPGA

Laboratories

  1. RTL design application to Xlinx FPGA board (Spartan3E)

Prerequisites

Boolean algebra, combinational and sequential logics, binary numbers, MOS transistors, arithmetic operators, Finite State Machine (Moore, Mealy)
Fixed point number representation, digital fourier transform, FIR and IIR digital filters design

Tests

  • E1 = final written exam (session 1), written, 1h30, only allowed document "Syntaxe VHDL"
  • TP = average of laboratory exams
  • CC = average of exams done in class or at home
  • E2 = final written exam (session 1), written, 1h30, only allowed document "Syntaxe VHDL"

Calendar

The course exists in the following branches:

  • Curriculum - Network and computer science - Semester 7
  • Curriculum - EIS - Semester 7
see the course schedule for 2020-2021

Additional Information

Course ID : 4AMCE410
Course language(s): FR

The course is attached to the following structures:

  • Team

You can find this course among all other courses.

Bibliography

RTL Hardware design using VHDL, coding for efficiency, portability and scalability, Pong. P. CHU, WILEY INTERSCIENCE

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Date of update June 25, 2015

Université Grenoble Alpes