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Verification and test of secure circuits - 5AMSE515

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  • Number of hours

    • Lectures : 24.0
    • Tutorials : 12.0
    • Laboratory works : 18.0
    ECTS : 6.0
  • Officials : David HELY, Vincent BEROULLE

Goals

At the end of the lecture, the students will be able to verify, to test digital architectures and to analyse the vulnerabilities of embedded systemes. Then, they will be able to perform attacks and to design appropriate countermeasures.


Contact David HELY, Vincent BEROULLE

Content

  1. Verification and test of digital systems
    1. Introduction
      1. Context and issues
      2. Verification vs Test
      3. DO-254 Standard
    2. Harwdware systems verification
      1. Simulation
      2. Emulation & Prototyping
    3. Hardware Testing
      1. Defects and faults modeling
      2. Automatic Test Pattern Generation (ATPG)
      3. Design for Test and Bult-in-Self-Test (DfT, BIST)
      4. Digital board testing (boundary scan)
  2. HW/SW Verification
    1. Microelectronic context and trends (SoC, MPSOC)
    2. SoC design flow
      1. Hardware/Software Co-design approach
      2. Plateform based design
    3. Introduction to SystemC
      1. Starting with SystemC
      2. Communication channels (Fifo, Mutex, Semaphore)
      3. New abstraction level : Transaction Level Modeling (TLM)
    4. Co-verification of Hardware and Software systems
      1. Context et definitions
      2. Co-verification approaches based on ISS, BFM, TLM, and emulation
      3. Criteria to choose a verification approach
  3. Hardware Security
    ##Introduction
    ##Cryptography basis
    1. Hardware Vulnerabilities
      1. Fault Attacks
      2. Side Chanel Attacks
      3. Integrated Circuit Trustworthiness
        ##Countermeasures
        ##Security Certification
        ##Case studies
      4. Smartcard
      5. FPGA

Laboratories

  • TP1 : VHDL & PSL Simulation with QuestaSim (Mentor GraphiCs)
  • TP2 : Simulation vs "prototyping and integrated logical analyzer" ChipScopePro (Xilinx)
  • TP3 : SRAM embedded memory test on FPGA Spartan 3 card (Xilinx)
  • TP1 : On the use of communication channels (Fifo, Mutex, Semaphore) to model a communication architecture
  • TP2 : SoCLib - "Emulation of a Hardware/Software architecture used for image processing"


Prerequisites

Neccessary: Hardware Description Language (HDL, verilog or VHDL) for simulation (testbench) and design, logical synthesis, FPGA, processor architecture (processor models, instruction set architecture), C programming

Ideally: bases of object oriented programming

Tests

E1 = Terminal Exam, First session, written, 3h, only document allowed "syntaxe VHDL", no calculator
TP = average of laboratory exams
E2 = Exam, Second session, written 3h, only document allowed "syntaxe VHDL", no calculator



Calendar

The course exists in the following branches:

  • Curriculum - - Semester 5
  • Curriculum - EIS - Semester 5
  • Curriculum - EIS (Apprenticeship) - Semester 5
see the course schedule for 2017-2018

Additional Information

Curriculum->->Semester 5
Curriculum->EIS ->Semester 5
Curriculum->EIS (Apprenticeship)->Semester 5

Bibliography

  • Writing testbenches – functional verification of HDL models, Kluwer, Janick Bergeron
  • Comprehensive functional verification, Bruce Wile, Elsevier, 2005
  • A practical introduction to PSL, Cindy Eisner, Dana Fisman, Springer
  • Security and Embedded Systems, Vol. 2 by Dimitrios Nikilaou Serpanos (Editor), Ran Giladi, R. Giladi (Editor)

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Date of update January 10, 2018

French
ESISAR
Grenoble INP - Esisar
50 rue Barthélémy de Laffemas CS 10054
​​​​​​​26902 Valence Cedex 09 - France
Tél : 04 75 75 94 00 - Fax : 04 75 43 56 42
 
 
        
Grenoble INP Institut d'ingénierie Univ. Grenoble Alpes