> Study at Esisar > MISTRE Master
The objective of this course is give to each student the minimal knowledge to design or choose a processor for a targeted application.
The students will learn the hardware architecture of a SOPC system and the associated software development to exploit the performance
of these systems.
This course is mainly divided into 2 parts. In the first one, the students will design a complex system composed of a
main processor and different peripherals linked by a bus using a Xilinx Zync 7000 chip. The second part deals with the NEON engine
located inside the main processor of the Zync 7000. This engine adds a new instruction set allowing to realize multiple operations
in parallel.
Introduction to System On Chip
Introduction to NEON
This course contains 2CM and 12TP and 1 Exam.
E1: Exam (1st session): Written exam 1h30, without documents, without calculator
E2: Exam (2nd session): Written exam 1h30, without documents, without calculator
TP: Labs
At the end of the lecture, the students will be able to verify and to test digital secure or critical architectures, and to analyze the robustness of embedded systemes.
General objectives:
*To be able to verify the functionalities of a design
*To be able to test its fabrication
*To be able to analyze the safety and security vulnerabilities of embedded systems
Specific objectives:
*Functional verification techniques
*Testbenches writing, qualification, assertions, emulation, prototyping, formal approaches
for FPGA or ASIC design flows
*Hardware testing
*Fault modeling, test pattern generation, DfT, JTAG
*On-line Printed Circuit Board (PCB) testing
*Robustness and vulnerability analyses
*To be able to choose the most adapted techniques for verification and test
*I Introduction
**A Context and Issues
**B Verification vs Test
**C Example of Aeronautical Standard DO-254
*II Hardware Verification
**A Hardware Simulation
***a languages, simulators and levels of abstraction
***b black/white box verifications
***c qualification
***d robustness measurement by fault simulation
***e writing testbench in VHDL (behavioural)
***f assertions (assert, OVL, PSL)
**B Formal verification
***a equivalence checking
***b property/model checking
**C Hardware testing
***a failures and hardware fault models
***b design for test and self test (DfT & BIST)
***c boundary scan
**C Security validation
***a fuzz testing
***b reuse of verification tools
*III Hardware/Software System Co-Verification (HW/SW)
**A Introduction
**B Hardware/Software Partitioning
***a objectives
***b tools (hardware accelerators, high-level synthesis, system design flow)
**C Hardware/software co-development
***a objectives and issues
***b solutions (co-simulation, FPGA prototyping, virtual prototyping)
**D Hardware/Software Co-Verification
***a objectives and solutions
Practical work
Project 1 : VHDL simulation & PSL assertions with QuestaSim (Mentor GraphiCs)
Project 2: Hardware/software co-verification based on virtual prototyping
Mandatory: Hardware Description Language (HDL, verilog or VHDL) for simulation (testbench) and design, logical synthesis, FPGA, processor architecture (processor models, instruction set architecture), C programming
Expected: bases of object oriented programming
E1 = Terminal Exam, First session, written, 2h, only document allowed "syntaxe VHDL", no calculator
TP = average of laboratory exams
E2 = Exam, Second session, written 2h, only document allowed "syntaxe VHDL", no calculator
computer architecture, digital electronics, VHDL/Verilog, signal processing, C programming, embedded system design and test
continuous assessment 25% Labs 25% Final Exam 50%
Students should be able to :
Course content
I. Introduction
II. Fault-tolerance: redundancy techniques
III. Fault prediction: dependability evaluation techniques
IV. Fault elimination: Software testing
V. Introduction to software security: vulnerabilities and protections
VI. Summary: safety and security
Tutoriel content
Lab works
E1: session 1 final exam (written exam, 3h00, closed books, allowed calculator)
TP: 1 mark
E2: session 2 exam (written exam, 1h30, closed books, allowed calculator)
Assess and enhance:
Groups consist of at least 4 students following different specialties.
Subjects (open and multidisciplinary) are offered by responsible of 5th year module.
The job is done by each group independently; groups have access to the SACCO platform and TP classrooms of the school.
P1 = Mean of report evaluation and oral presentation
After the course, the student should be able to:
Hardware design courses: digital design, VHDL, FPGA.
Embedded application design.
E1: result of end-term written exam (90 min)
E2: individual oral examination (30 min)
CC: semester-long assessment
Documents and calculators authorized for all exams
This course reviews the past and present results in the area of decentralized control of complex dynamical systems. Elements from control theory and optimization are merged in order to provide useful tools which will be further applied to various problems involving multi-agent dynamical systems and interconnected systems in general.
An emphasis is laid on centralized vs distributed vs decentralized approaches, decomposition, information structure constraints, the stabilization and the tracking performances of each agent, robustness. The presented theory answers the fundamental questions of how to break down a given control problem into manageable subproblems which are only weakly related to each other and can be solved independently.
The tools the students will acquire during the course in optimization-based control (via distributed/hierarchical approaches) will be used for some application benchmarks like control and coordination of multiple (aerial, aquatic) drones, energy management in DC microgrid systems and water distribution networks.
1 An optimization-based approach for control of complex systems
1.1 Introduction to the control of complex systems
1.2 Optimization-based control
1.3 Generic prediction models
1.4 Generation of a reference trajectory/profile
1.5 Set-theoretic elements
1.6 Mixed-integer representations in control design
2 Challenges in decentralized control
2.1 Decentralization
2.2 Decomposition
2.3 Coupling constraints
2.4 Information exchange
3 Cooperative control of multi-agent dynamical systems
3.1 System description
3.2 Collision avoidance formulation
3.3 Area coverage for multi-agent systems in multi-obstacle environment
3.4 A tight configuration of multi-agent formation
3.5 Centralized MPC
3.6 Distributed MPC
3.7 Decentralized MPC
4 Stability and robustness analysis
4.1. Stability ingredients
4.2. Tube MPC introduction
5 Examples, simulations, benchmarks and applications
5.1 Flight control experiments of Unmanned Aerial Vehicles (UAVs)
5.2 Connectivity maintenance for Unmanned Surface Vehicles (USVs)
5.3 Hierarchical control for DC microgrid energy management
5.4 Decentralized supervision and control of water networks
The course is intended for master students in applied science with a major in control. A basic knowledge in control theory (state-space representation) and Matlab/Python/C programming are required.
This module will also give some insights on the research field and will provide direction for students who want to start a PhD thesis.
N1= 30%xTP + 70%xFinalExam
N2= 100%FinalExam
Nconf = 100% FinalExam
FinalExam = Oral examination
General objectives of the course:
-to consolidate language structure and both oral and written skills
-to give students the tools needed to operate in daily situations during their stay in France
Pedagogical objectives:
-help students become independent in a variety of daily situations in France
France: understanding (listening and reading) info about France
Auvergne Rhône-Alpes Region (Lyon and Grenoble)
Drôme and Ardèche: understanding basic documents (tourism, the economy, culture)
Studying and working in France
Writing a CV and a cover letter
Making appointments over the phone
Job interviews
New Technologies
None
Methods of Evaluations : tests and quizzes
Date of update May 4, 2021