Number of hours
- Lectures 9.0
- Projects -
- Tutorials 4.5
- Internship -
- Laboratory works 9.0
- Written tests -
ECTS
ECTS 2.0
Goal(s)
Design of simple digital system on programmable components (CPLD and FPGA)
Understanding basic componentsof computer.
Responsible(s)
Vincent BEROULLE
Content(s)
*"support" lessons (for CPGE students only)*
*Fundamental of digital electronics
**Binary numbers & arithmetic
**Boolean algebra & logical components
**Combinational logic & arithmetic circuits
**Sequential logic & finite state machines
Digital circuits design
*#Introduction to VHDL
*#VHDL basis
*#Programmable components
Laboratories
Simulation and logical synthesis of simple functions written in VHDL
See content of the support classes for CPGE students
Algorithm, programming basis
Test
CC = Mean of laboratory marks and homeworks
E1 = Terminal Exam, First session, written, 1h30, only document allowed "syntaxe VHDL", no calculator
E2 = Exam, Second session, written 1h30, only document allowed "syntaxe VHDL", no calculator
Calendar
The course exists in the following branches:
- Curriculum - Network and computer science - Semester 5
- Curriculum - EIS - Semester 5
Additional Information
Course ID : 3AMCE312
Course language(s): 
The course is attached to the following structures:
You can find this course among all other courses.
Bibliography
*VHDL, du langage au circuit, du circuit au langage, J. Weber, M. Meaudre, Masson
*Initiation au langage VHDL, Michel Aumiaux, Dunod
*VHDL, langage, modélisation, synthèse, Airiau, Bergé, Olive, Rouillard, P. P. Romandes
*Circuits numériques et synthèse logique, un outil: VHDL, J.Weber, M. Meaudre, Masson
VHDL, Introduction à la synthèse logique, P. Larcher, Eyrolles
What is a grande école ?
French engineering curriculum
