Hardware Architecture Design with FPGA - 4AMCE410

Goal(s)

At the end of the lecture, the students will be able to design complex digital systems into programmable components (CPLD ou FPGA)

Content(s)

Lecture chapters

1. Introduction
   1. Programmable components
   2. Context and issues
   3. Design flow
   4. Signal vs. variable
   5. Why to use programmable components ?
2. Design of synchronous digital systems and GALS
   1. GALS design
   2. Metastability and signal transmission between clock domains
3. Methods for RTL Synthesis
   1. Synthesis directives issues (ressources sharing, FSM coding...)
   2. Regular design
   3. Random design (FSM-based descriptions)
   4. RTL design : from flow chart to ASMD
4. Digital Signal Processing with FPGA

Laboratories

1. RTL design application to Xlinx FPGA board (Spartan3E)

Boolean algebra, combinational and sequential logics, binary numbers, MOS transistors, arithmetic operators, Finite State Machine (Moore, Mealy)
Fixed point number representation, digital fourier transform, FIR and IIR digital filters design