Hardware Architecture Design with FPGA - 4AMCE419

Lecture chapters

1. Introduction
   1. Programmable components
   2. Context and issues
   3. Design flow
   4. Signal vs. variable
   5. Why to use programmable components ?
2. Design of synchronous digital systems and GALS
   1. GALS design
   2. Metastability and signal transmission between clock domains
3. Methods for RTL Synthesis
   1. Synthesis directives issues (ressources sharing, FSM coding...)
   2. Regular design
   3. Random design (FSM-based descriptions)
   4. RTL design : from flow chart to ASMD
4. Digital Signal Processing with FPGA

Laboratories

1. RTL design application to Xlinx FPGA board (Spartan3E)

Boolean algebra, combinational and sequential logics, binary numbers, MOS transistors, arithmetic operators, Finite State Machine (Moore, Mealy), Fixed point number representation, digital fourier transform, FIR and IIR digital filters design

• E1 = final written exam (session 1), written, 1h30, only allowed document "Syntaxe VHDL", no calculator
• TP = average of laboratory exams
• CC = average of exams done in class or at home
• E2 = final written exam (session 1), written, 1h30, only allowed document "Syntaxe VHDL", no calculator

• RTL Hardware design using VHDL, coding for efficiency, portability and scalability, Pong. P. CHU, WILEY INTERSCIENCE
• VHDL, du langage au circuit, du circuit au langage, J. Weber, M. Meaudre, Masson
• Initiation au langage VHDL, Michel Aumiaux, Dunod
• VHDL, langage, modélisation, synthèse, Airiau, Bergé, Olive, Rouillard, P. P. Romandes
• Circuits numériques et synthèse logique, un outil: VHDL, J.Weber, M. Meaudre, Masson
• VHDL, Introduction à la synthèse logique, P. Larcher, Eyrolles
• A guide to VHDL, second edition, Stanley Mazor - P. Lang Straat, Kluwer
• VHDL Programming, with advanced topics, L. Baker, Wiley
• VHDL, second edition, Douglas Perry, Mc Graw-Hill Series