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Hardware Architecture Design with FPGA - 4AMCE419

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  • Number of hours

    • Lectures : 12.0
    • Tutorials : 13.5
    • Laboratory works : 15.0
    ECTS : 2.0

Goals

At the end of the lecture, the students will be able to design complex digital systems into programmable components (CPLD ou FPGA)

Contact Vincent BEROULLE

Content

Lecture chapters

  1. Introduction
    1. Programmable components
    2. Context and issues
    3. Design flow
    4. Signal vs. variable
    5. Why to use programmable components ?
  2. Design of synchronous digital systems and GALS
    1. GALS design
    2. Metastability and signal transmission between clock domains
  3. Methods for RTL Synthesis
    1. Synthesis directives issues (ressources sharing, FSM coding...)
    2. Regular design
    3. Random design (FSM-based descriptions)
    4. RTL design : from flow chart to ASMD
  4. Digital Signal Processing with FPGA

Laboratories

  1. RTL design application to Xlinx FPGA board (Spartan3E)


Prerequisites

Boolean algebra, combinational and sequential logics, binary numbers, MOS transistors, arithmetic operators, Finite State Machine (Moore, Mealy), Fixed point number representation, digital fourier transform, FIR and IIR digital filters design

Tests

  • E1 = final written exam (session 1), written, 1h30, only allowed document "Syntaxe VHDL", no calculator
  • TP = average of laboratory exams
  • CC = average of exams done in class or at home
  • E2 = final written exam (session 1), written, 1h30, only allowed document "Syntaxe VHDL", no calculator


Additional Information

Curriculum->EIS (Apprenticeship)->4A_APPRENTI

Bibliography

  • RTL Hardware design using VHDL, coding for efficiency, portability and scalability, Pong. P. CHU, WILEY INTERSCIENCE
  • VHDL, du langage au circuit, du circuit au langage, J. Weber, M. Meaudre, Masson
  • Initiation au langage VHDL, Michel Aumiaux, Dunod
  • VHDL, langage, modélisation, synthèse, Airiau, Bergé, Olive, Rouillard, P. P. Romandes
  • Circuits numériques et synthèse logique, un outil: VHDL, J.Weber, M. Meaudre, Masson
  • VHDL, Introduction à la synthèse logique, P. Larcher, Eyrolles
  • A guide to VHDL, second edition, Stanley Mazor - P. Lang Straat, Kluwer
  • VHDL Programming, with advanced topics, L. Baker, Wiley
  • VHDL, second edition, Douglas Perry, Mc Graw-Hill Series

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Date of update June 25, 2015

French
Grenoble INP - Esisar
Grenoble INP - Esisar
50 rue Barthélémy de Laffemas CS 10054
​​​​​​​26902 Valence Cedex 09 - France
Tél : 04 75 75 94 00 - Fax : 04 75 43 56 42
 
 
         
Université Grenoble Alpes